Field of the Invention
The present invention relates to an image processing apparatus and an image processing interface circuit. The image processing interface circuit is connected to a module core for executing predetermined image processing.
Description of the Background Art
In an image processing apparatus, conventionally, a DMAC (Direct Memory Access Controller) is utilized for a data transfer between an image processing module core and a DRAM (Dynamic Random Access Memory). For instance, dedicated DMACs are connected to the respective module cores and are directly connected to buses respectively.
Moreover, there is known a module core for performing image processing on a so-called macroblock unit. For instance, it is possible to select a size of a macroblock from 16×16, 16×8, 8×16, 8×8, 8×4, 4×8, and 4×4 pixels in H.264. Such an image processing module core performs access to a DRAM, that is, reading and writing on the macroblock unit.
Moreover, Japanese Patent Application Laid-Open No. 2007-74412 discloses another example of the related art.
With the structure in which the dedicated DMAC is provided in each of the module cores, however, a large number of DMACs are present so that a chip area is increased.
When the access to the DRAM is performed on the macroblock unit, moreover, the efficiency of memory access is reduced. For instance, one line has only eight bytes in a macroblock having 4×4 pixels in 8-bit YUV422. For this reason, an ROW address of the DRAM is to be switched with reading of only eight bytes. When a read request is issued every line of the macroblock, moreover, consumption of a bus band is increased due to a large number of request issues. These respects are the same in writing.